FIG. 1 illustrates conventional signal output circuitry 100 having a signal output signal pad 102 that is coupled to an output signal node 107 of a High Voltage (HV) output buffer circuit 170 that includes HV complementary metal-oxide semiconductor (CMOS) driver circuitry coupled between positive high voltage supply rail VDDH and negative supply rail VSS (ground) as shown. Output buffer circuit 170 includes a HV P-channel MOSFET (PMOS) output transistor 110 and a HV N-channel MOSFET (NMOS) output transistor 112 that each have a gate coupled to an internal output control circuit 114. Signal pad 102 is coupled at node 107 between the HV PMOS output transistor 110 and the HV NMOS output transistor 112 of buffer circuit 170. As further illustrated, signal output circuitry 100 is configured with a high voltage electrostatic discharge (ESD) protection device that includes an N-channel insulated-gate bipolar transistor (NiGBT) device 180 that is coupled between signal pad 102 and ground or VSS at node 103 as shown to form an embedded parasitic silicon controlled rectifier (SCR). NiGBT device 180 includes a NMOS transistor M1, with a PNP bipolar transistor Q1 coupled as shown between signal pad 102 and ground. NMOS transistor M1 itself is coupled between the base of PNP transistor Q1 and ground, with a parasitic NPN transistor Q2 also coupled between the base of PNP transistor Q1 and ground. As shown, the gate of NMOS transistor M1 is also coupled to ground.
The occurrence of a positive ESD event 190 on signal pad 102 causes a corresponding rise in voltage of the drift region due to the forward biased emitter-base diode of PNP transistor Q1. This voltage appears across the entire N-type drift region which begins at the base of Q1 and terminates at the drain of M1. An effective drift resistance RDRIFT exists between these two points where the drift region is generally engineered to be very lightly doped. The ESD potential which was originally applied to signal pad 102 now appears across the drain body diode of M1 which is reverse biased. As the ESD potential continues to rise, eventually the drain-body diode of M1 will avalanche breakdown, thereby generating electron-hole pairs in the process. When the generated holes flow to ground through the substrate resistance RS, an elevation in substrate potential occurs that acts to forward bias the base-emitter junction of parasitic NPN Q2, thereby turning this device on which causes collector current to flow in Q2. The collector current in Q2 in turn causes base and collector current to flow in Q1. The collector current in Q1 acts to further elevate the potential across RS which causes a further increase in base and collector current in Q2. A positive feedback loop is formed and the parasitic SCR turns on and shunts the ESD current from signal pad 102 to ground. The voltage at which the parasitic SCR turns on is called VT1 and is set entirely here by the breakdown voltage of the drift region to body-diode of transistor M1. In general VT1 must be set higher than the normal operating voltage of the output buffer circuit 170 that NiGBT device 180 is protecting. Often times in high voltage processes, the VTI of the protection device is also very close in magnitude to the voltage at which the HV NMOS and HV PMOS output devices themselves are damaged and great care must be taken to ensure that the ESD device triggers before an output buffer device.